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HANBit
HMS25632M8G/Z8
HAN BIT
SRAM MODULE 1Mbyte (256K x 32-Bit) Part No.
HMS25632M8, HMS25632Z8
GENERAL DESCRIPTION
The HMS25632M8G/Z8 is a high-speed static random access memory (SRAM) module containing 262,144 words organized in a x32-bit configuration. The module consists of eight 256K x 4 SRAMs mounted on a 64-pin, double-sided, FR4-printed circuit board. PD0 and PD1 identify the module's density allowing interchangeable use of alternate density, industry- standard modules. Four chip enable inputs, (/CE1, /CE2, /CE3 and /CE4) are used to enable the module's 4 bytes independently. Output enable (/OE) and write enable (/WE) can set the memory input and output. Data is written into the SRAM memory when write enable (/WE) and chip enable (/CE) inputs are both LOW. Reading is accomplished when /WE remains HIGH and /CE and output enable (/OE) are LOW. For reliability, this SRAM module is designed as multiple power and ground pin. All module components may be powered from a single +5V DC power supply and all inputs and outputs are fully TTL-compatible.
FEATURES
Part Identification
-HMS25632M8G : 64Pin SIMM Design, Gold Plate Lead -HMS25632Z8 : 64Pin ZIP Design Pin-Compatible with the HMS25632M8G
PD0 DQ0 DQ1 DQ2 DQ3 Vcc A7 A8 A9 DQ4 DQ5 DQ6 DQ7 /WE A14 /CE1 /CE3 A16 Vss DQ16 DQ17 DQ18 DQ19 A10 A11 A12 A13 DQ20 DQ21 DQ22 DQ23 Vss
PIN ASSIGNMENT
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 Vss PD1 DQ8 DQ9 DQ10 DQ11 A0 A1 A2 DQ12 DQ13 DQ14 DQ15 Vss A15 /CE2 /CE4 A17 /OE DQ24 DQ25 DQ26 DQ27 A3 A4 A5 Vcc A6 DQ28 DQ29 DQ30 DQ31
Access times: 8, 10, 12, 15and 20ns High-density 1MByte design High-reliability, high-speed design Single + 5V 0.5V power supply Easy memory expansion with /CE and /OE functions All inputs and outputs are TTL-compatible Industry-standard pinout
OPTIONS
Timing
8ns access 10ns access 12ns access 15ns access 20ns access
MARKING
-8 -10 -12 -15 -20 M Z
Packages
64-pin SIMM 64-pin ZIP
ZIP TOP VIEW
PD0 = Vss PD1 = Vss
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HANBit Electronics Co.,Ltd.
HANBit FUNCTIONAL BLOCK DIAGRAM
32 18 A0-17 DQ 0-3 /WE /OE
HMS25632M8G/Z8
DQ0 - DQ31 A0 - A17
A0-17 DQ 4-7 /WE /OE
U1
/CE
U5
/CE
/CE1 A0-17 DQ 8-11 /WE /OE /WE A0-17 DQ12-15 /OE
U2
/CE
U6
/CE
/CE2 A0-17 DQ16-19 /WE /OE /WE A0-17 DQ20-23 /OE
U3
/CE
U7
/CE
/CE3 A0-17 /WE /OE DQ24-27 /WE /OE /WE A0-17 DQ28-31 /OE
U4
/CE
U8
/CE
/CE4
PRESENCE-DETECT PD0 = Vss PD1 = Vss
TRUTH TABLE
MODE STANDBY NOT SELECTED READ WRITE /OE X H L X /CE H L L L /WE X H H L OUTPUT HIGH-Z HIGH-Z Dout Din POWER STANDBY ACTIVE ACTIVE ACTIVE
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HANBit ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN,OUT VCC PD TSTG
HMS25632M8G/Z8
RATING -0.5V to Vcc+0.5V -0.5V to +7.0V 8W -65oC to +150oC
0oC to +70oC Operating Temperature TA Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage * SYMBOL VCC VSS VIH VIL MIN 4.5V 0 2.2 -0.5*
( TA=0 to 70 o C ) TYP. 5.0V 0 MAX 5.5V 0 Vcc+0.5V** 0.8V
VIL(Min.) = -2.0V (Pulse Width 10ns) for I 20 mA
** VIH(Min.) = Vcc+2.0V (Pulse Width 10ns) for I 20 mA
DC AND OPERATING CHARACTERISTICS (1)(0oC TA 70 oC ; Vcc = 5V 0.5V )
PARAMETER Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage * Vcc=5.0V, Temp=25 oC TEST CONDITIONS VIN = Vss to Vcc /CE=VIH or /OE =VIH or /WE=VIL VOUT=Vss to VCC IOH = -4.0Ma IOL = 8.0mA SYMBO L ILI IL0 VOH VOL MIN -2 -2 2.4 0.4 MAX 2 2 UNITS A A V V
DC AND OPERATING CHARACTERISTICS (2)
MAX DESCRIPTION Power Supply Current: Operating Power Supply Current: Standby TEST CONDITIONS Min. Cycle, 100% Duty /CE=VIL, VIN=VIH or VIL, IOUT=0mA Min. Cycle, /CE=VIH f=0MHZ, /CEVCC-0.2V, VIN VCC-0.2V or VIN0.2V SYMBOL ICC ISB ISB1 -12 70 30 5 -15 68 30 5 -20 65 30 5 UNIT mA mA mA
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HANBit Electronics Co.,Ltd.
HANBit CAPACITANCE
DESCRIPTION Input /Output Capacitance Input Capacitance TEST CONDITIONS VI/O=0V VIN=0V SYMBOL CI/O CIN
HMS25632M8G/Z8
MAX 8 6
UNIT pF pF
* NOTE : Capacitance is sampled and not 100% tested
AC CHARACTERISTICS (0oC TA 70 oC ; Vcc = 5V 0.5V, unless otherwise specified)
TEST CONDITIONS
PARAMETER Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Output Load VALUE 0 to 3V 3ns 1.5V See below
Output +5V
Load
Output Load (B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5V
480 DOUT 255 30pF* DOUT 255
480 5pF*
READ CYCLE
-12 PARAMETER Read Cycle Time Address Access Time Chip Select to Output Output Enable to Output Output Enable to Low-Z Output Chip Enable to Low-Z Output Output Disable to High-Z Output Chip Disable to High-Z Output Output Hold from Address Change
SYMBOL MIN MAX MIN MAX MIN MAX
-15
-20
UNIT
tRC tAA tCO tOE tOLZ tLZ tOHZ tHZ tOH
12 12 12 6 0 3 0 0 3 6 6
15 15 15 7 0 3 0 0 3 7 7
20 20 20 9 0 3 0 0 3 9 9
ns ns ns ns ns ns ns ns ns
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HANBit Electronics Co.,Ltd.
HANBit
Chip Select to Power Up Time Chip Select to Power Down Time tPU tPD 12 0
HMS25632M8G/Z8
0 15 20 ns ns
WRITE CYCLE
PARAMETER Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End of Write to Output Low-Z -12
SYMBOL MIN MAX MIN MAX MIN MAX
-15
-20
UNIT
tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW
12 8 0 8 8 0 0 6 0 3 6
15 9 0 9 9 0 0 7 0 3 7
20 10 0 10 10 0 0 8 0 5 9
ns ns ns ns ns ns ns ns ns ns
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE( Address Controlled) ( /CE = /OE = VIL , /WE = VIH)
tRC Address tAA tOH Data out
Previous Data Valid Data Valid
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HANBit Electronics Co.,Ltd.
HANBit
TIMING WAVEFORM OF READ CYCLE ( /CE Controlled )
tRC Address tAA /CE tLZ(4,5) /OE tOLZ Data Out Vcc Supply Current High-Z
Data Valid
HMS25632M8G/Z8
tHZ(3,4,5) tCO tOHZ tOE tOH
lCC lSB
tPU 50%
tPD 50%
Notes (Read Cycle)
1. /WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, t HZ (max.) is less than tLZ (min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with /CE = VIL. 7. Address valid prior to coincident with /CE transition low.
TIMING WAVEFORM OF WRITE CYCLE (/OE = Clock )
tWC
Address
tAW tWR(5)
/OE
tCW(3)
/CE
tAS(4) tWP(2)
/WE
tDW tDH Data Valid tOHZ(6) High-Z
Data In
Data Out
High-Z
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HANBit Electronics Co.,Ltd.
HANBit
TIMING WAVEFORM OF WRITE CYCLE (/OE Low Fixed )
tWC
HMS25632M8G/Z8
Address
tAW tCW(3) tWR(5)
/CE
tAS(4) tOH tWP(2) tDW tDH
/WE
Data In
High-Z tWHZ(6,7) tOW High-Z(8)
(10)
(9)
Data Out
Notes (Write Cycle)
1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among /CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of /CE going low to the end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CE, or /WE going high. 6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state. 9. DOUT is the read data of the new address. 10. When /CE is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
/CE H L L L /WE X* H H L /OE X H L X MODE Not Select Output Disable Read Write I/O PIN High-Z High-Z DOUT DIN SUPPLY CURRENT l SB, l SB1 lCC lCC lCC
Note: X means Don't Care
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HANBit Electronics Co.,Ltd.
HANBit PACKAGING DIMMENSIONS
SIMM Design
98.04 mm
HMS25632M8G/Z8
10.16 mm 6.35 mm 16 mm
1
2.03 mm 1.02 mm 6.35 mm 6.35 mm 85.09 mm 1.27 mm
64
3.34 mm
0.25 mm MAX
2.54 mm MIN
1.290.08 mm
Gold: 1.040.10 mm 1.27 Solder: 0.9140.10 mm
(Solder & Gold Plating Lead)
ZIP Design
89 mm CUT 1.5 mm
14 mm 1 6 mm 64
2.54 mm 2 mm 90 mm
40 mm
1.290.08 mm
2.5 mm
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HANBit Electronics Co.,Ltd.
HANBit
HMS25632M8G/Z8
ORDERING INFORMATION
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HMS
HANBit Memory Modules SRAM
256 32 M 8G -15
15ns Access Time Component, Gold SIMM x32bit 256K
1. - Product Line Identifier HANBit ------------------------------------------------------ H 2. - Memory Modules 3. - SRAM 4. - Depth : 256K 5. - Width : x 32bit 6. - Package Code SIMM ------------------------------------------------------- M ZIP ------------------------------------------------------- Z 7. - Number of Memory Components ---8 , Gold Plate Lead --G 8. - Access time 8 ----------------------------------------------------------- 8ns 10 ----------------------------------------------------------- 10ns 12 ----------------------------------------------------------- 12ns 15 ----------------------------------------------------------- 15ns 20 ----------------------------------------------------------- 20ns
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